rustamc
@RustamC
About
Researcher. Scope of activity: EDA, P&R, STA, SI
Skills & Technologies
Projects & Repositories
Recent public projects and repositories from this profile.
macro-place-challenge-2026
No project description available.
crates-index
Registry index for Substrate Labs.
circuit_training_openlane
Instructions on how to run Circuit Training in OpenLane flow
open-src-cvc
Mirror of tachyon-da cvc Verilog simulator
toolchain-iverilog
Verilog:seedling: Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
transistor_counter
RustSimple transistor counter in Verilog gate-level netlist using data from CDL