Nitish

Repository for tracking my daily progress on learning Verilog/FPGA

Designing a UART module in Verilog HDL

Learning FPGA, yosys, nextpnr, and RISC-V

Electrical design, firmware and Python library for a low noise high resolution wide bandwidth Linear CCD and Teensy 4 (MCU) implementation with trigger, gate, and sync.

No project description available.

An experimental gesture recognition program made using OpenCV and Mediapipe