Bhavin Umatiya
@Bhavin-umatiya
About
RTL Design & Verification (SystemVerilog/UVM) | Embedded Systems | Linux Foundation Contributor (ROS 2, Zephyr)
Skills & Technologies
Projects & Repositories
Recent public projects and repositories from this profile.
Bhavin-umatiya
No project description available.
ZCU104-ViT-Hardware-Accelerator
Jupyter Notebook50.7x latency-optimized heterogeneous Vision Transformer (DeiT) hardware accelerator built on the Xilinx ZCU104 FPGA using DPU + custom HLS IPs.
zcu104-adaptive-video-pipeline
AI-driven bandwidth management for embedded video surveillance. YOLOv4 on the Xilinx DPU + 3-zone ROI masking + hardware H.264 (VCU) encoding on ZCU104.
Latency-Optimized-Heterogeneous-AI-Accelerator
TclLatency-Optimized Heterogeneous AI Accelerator for Vision Transformers (ViT)
AXI4-CXL-Memory-Controller
SystemVerilogUVM-Verified CXL.mem Type 3 Memory Expander Controller. Dynamically bridges high-bandwidth CXL.mem cachelines (512-bit) to AXI4 (32-bit) with concurrent SystemVerilog Assertions (SVA) and functional coverage closure.
lfx-risc-v-challenge
CNo project description available.